VisualApplets
Manuals

Sidebar	\| Next
Content \| Home
PDF \| Print \| Contact us

VisualApplets

Table of Contents

User Manual

Introduction

VisualApplets
How to Use This Documentation
System Requirements

The User Interface of VisualApplets

Main Window
Information Panel
Library Panel
Adapting the Program Window
Multiple Processes
Keyboard Shortcuts
Command Line Options
Print / Screenshot

Getting Started

Creating Your First Applet
Running Your Applet on Hardware
Further Reading

Basic Functionality

Basic Principles
Workflow
Data Flow
Entering a Design
Hierarchical Boxes
Rules of Links
Parametrization
Simulation
System Settings
Design Settings
FPGA Resource Estimation
Allocation of Device Resources
Design Rules Check
Build
Framegrabber SDK
Error Reporting

Advanced Functionality

Scripting
User Libraries
Custom Operator Libraries
Target Hardware Porting
Migration from Older Versions

Embedded VisualApplets (eVA)

Introduction
Common Interfaces for all Platforms
Defining the IP Core Properties
Embedding and Simulating the IP core
Runtime Software Interface
Licensing Model
Application Notes

Tutorial and Examples

Introduction

Hardware Applet: From Idea to Application

Workflow Description
Designing an Applet in VisualApplets
Building the Applet in VisualApplets
Running the Applet on Hardware

Basic Design Theory

Applet Parameterization
Multiple DMA Channel Designs
Synchronization of Asynchronous Image Pipelines

Basic Acquisition Designs for Varying Camera Types and Hardware Platforms

Basic Acquisition Examples for Camera Link Cameras for marathon, LightBridge and ironman Frame Grabbers
Basic Acquisition Examples for CoaXPress Cameras for marathon and ironman Frame Grabbers
Basic Acquisition Examples for Cameras for CoaXPress 12 imaFlex Frame Grabber

Processing Examples

Artificial Image Source
Binarization
Blob Detection
Color
Compression
Co-Processor
Debugging and Test
Difference Images
DMAFromPC
Fast Fourier Transform
Filter
Geometry
High Dynamic Range and Image Composition
Laser Detection
Lookup Table
Loop
Multiple Regions Of Interest
Object Features
Shading Correction
Trigger

Operator Examples

Functional Example for Specific Operators of Library Accumulator and Library Logic
Functional Example for Specific Operators of Library Synchronization: Dynamic Append and Cut
Functional Example for Specific Operators of Library Memory and Library Signal
Functional Example for Specific Operators of Library Memory and Library Signal
Functional Example for Specific Operators of Library Signal
Functional Example for Specific Operators of Library Synchronization, Base and Filter
Functional Example for Specific Operators of Library Arithmentics: Trigonometric Functions
Functional Example for Specific Operators of Library Color, Base and Memory
Functional Example for Specific Operators of Library Signal, Logic, Filter and Parameters

Parameter Library Examples

Parameter Redirection
Parameter Translation
User Library Parameter
Parameter Selection
Link Parameter Translation

Using Applets During Runtime

Filling LUT with Content With the Basler Framegrabber API

Operator Reference

Introduction

Library Overview

Library Accumulator

ColMax
ColMin
ColSum
Count
FrameMax
FrameMin
FrameSum
Histogram
ModuloCount
Register
RowMax
RowMin
RowSum

Library Arithmetics

ABS
ADD
ARCCOS
ARCCOT
ARCSIN
ARCTAN
ClipHigh
ClipLow
COS
COT
DIV
MULT
RND
SCALE
ShiftLeft
ShiftRight
SIN
SQRT
SUB
TAN

Library Base

Library Blob

Definition
Definition of Object Features
BlobDetector1D
BlobDetector2D
Blob_Analysis_1D
Blob_Analysis_2D

Library Color

BAYER3x3Linear
BAYER5x5Linear
ColorTransform
HSI2RGB
RGB2HSI
RGB2YUV
WhiteBalance
WhiteBalanceBayer

Library Compression

ImageBuffer_JPEG_Gray
JPEG_Encoder_Gray
JPEG_Encoder

Library Debugging

ImageAnalyzer
ImageStatistics
StreamAnalyzer
Scope
ImageInjector
ImageTimingGenerator
ImageFlowControl
StreamControl
ImageMonitor

Library Filter

DILATE
ERODE
FIRkernelNxM
FIRoperatorNxM
HitOrMiss
LineNeighboursNx1
MAX
MEDIAN
MIN
NumberOfHits
PixelNeighbours1xM
SORT

Library Logic

AND
CASE
CMP_AgeB
CMP_AgtB
CMP_AleB
CMP_AltB
CMP_Equal
CMP_NotEqual
IF
IS_Equal
IS_GreaterEqual
IS_GreaterThan
IS_InRange
IS_LessEqual
IS_LessThan
IS_NotEqual
NOT
OR
XNOR
XOR

Library Memory

CoefficientBuffer
CoefficientBufferMultiRoi (imaFlex)
FrameBufferMultiRoi (imaFlex)
FrameBufferMultiRoiDyn
FrameBufferRandomRead
FrameBufferRandomRead (imaFlex)
FrameMemory
FrameMemoryRandomRd
ImageBuffer
ImageBufferMultiRoI
ImageBufferMultiRoIDyn
ImageBufferSC
ImageFifo
KneeLUT
LineBuffer (imaFlex)
LineMemory
LineMemoryRandomRd
LUT
RamLUT
RamLUT (imaFlex)
ROM

Library Parameters

EnumParamReference
EnumParamTranslator
EnumVariable
FloatFieldParamReference
FloatParamReference
FloatParamTranslator
FloatVariable
IntFieldParamReference
IntParamReference
IntParamTranslator
IntVariable
IntFieldVariable
LinkProperties
LinkParamTranslator
StringParamReference
ResourceReference
IntParamSelector
FloatParamSelector

Library Hardware Platform

AppletProperties
BoardStatus
CameraControl
BaseGrayCamera
BaseRgbCamera
MediumGrayCamera
MediumRgbCamera
FullGrayCamera
FullRgbCamera
CLHSDualCamera
CLHSPulseIn
CLHSPulseOut
CLHSSingleCamera
CxpCamera
CxpCameraMultiTap
CxpAcquisitionStatus
CxpPortStatus
CxpRxTrigger
CxpTxTrigger
CXPDualCamera
CXPQuadCamera
CXPSingleCamera
DmaFromPC
DmaToPC
GPI
GPO
LED

Library Prototype

COUNTER
CustomSignalOperator
HWMULT
PackbitsRLE
TrgBoxLine
RGB2XYZ
XYZ2LAB

Library Signal

Library Synchronization

AppendImage
AppendImageDyn
AppendLine
AppendLineDyn
CutImage
CutLine
CreateBlankImage
ExpandLine
ExpandPixel
ImageValve
InsertImage
InsertLine
InsertPixel
IsFirstPixel
IsLastPixel
PixelReplicator
PixelToImage
RemoveImage
RemoveLine
RemovePixel
ReSyncToLine
RxImageLink
SourceSelector
SplitImage
SplitLine
SYNC
TxImageLink
Overflow

Library Transformation

FFT

Device Resources

Hardware Configuration of Supported Platforms
Device Resources of Supported Platforms
Shared Memory Concept

Bibliography

List of Figures

1. VisualApplets - From Idea to Image Processor in 15 Minutes
2. VisualApplets – Awarded Software Environment
3. Main Program Window
4. Operator not available for currently selected target hardware platform
5. The Information Panel
6. Project Info
7. Module Search
8. Module Search
9. Parameter Info
10. DRC Log Information
11. Build Log Information
12. Example: Displaying Information on the MergeKernel Operator
13. Library Panel with Operator Library on Display
14. Library Panel with Operator Library on Display
15. Undock via Context Menu
16. Undock via Float button
17. Re-docking Floating Windows
18. Opening the Split View
19. Split View
20. Configuring the number of displayed recent designs
21. Applet with Four Processes
22. Creating a New Process
23. VisualApplets Main Window
24. Start of a New Project
25. Dragging Operators from Libraries into the Design Window
26. Module Properties
27. Successful DRC
28. Build Settings for microEnable 5 / Xilinx Vivado
29. Simple VisualApplets Design
30. The Design Workflow
31. FPGA vs. CU Transfer/Processing Performance
32. Transferring and Processing Images in VisualApplets Data Pipeline
33. Simple VisualApplets Design
34. Parallelism for Clock Frequency of 125 MHz
35. Pixel Order
36. Model of a 2D Image Protocol
37. Model of a 1D Image Protocol
38. Model of an 0D Image Protocol
39. Start of a new Project
40. Edit Project Details
41. Menu Design, menu item Change FPGA Clock
42. Slider and spin box for selecting FPGA clock frequency
43. Operator Libraries
44. Error message in case an operator is not applicable for another hardware platform
45. Example of a Hierarchical Box
46. Window tabs of the design window
47. Highlighting a Port
48. Highlighting a Port
49. Entering a port name
50. Renamed ports of a hierarchical box
51. Highlighting a port
52. Reordered input ports of a hierarchical box
53. O-Type Network
54. Failing O-Type Network
55. Display of not correctly synchronized data flow in VisualApplets 2.2 and higher
56. M-type and O-type Network
57. M-type Operator with One Synchronous Input Group
58. M-type Operator with Asynchronous Inputs
59. Synchronization of Independent Sources
60. Deadlock at SYNC, figure a
61. Deadlock at SYNC, figure b
62. Fixed Deadlock
63. Deadlock Avoided
64. Bandwidth Limitation
65. Bandwidth Limitation Compensated
66. Infinite Source Connection Error
67. Infinite Source Connection OK
68. Infinite source conversion module (Buffer1) connected to a non-infinite source
69. O-type module with signal link inputs, sourced by different M-type modules
70. The Parameter Info View
71. Parameter Info
72. Module Properties Dialog
73. Field Parameter Edit Window
74. Function Dialog to Edit Field Parameters
75. Disabled Parameters
76. Autocompletion for Reference Parameters
77. Autocompletion in "Enter data for <operator>/<parameter> Dialog
78. Syntax Highlighting in "Enter data for <operator>/<parameter> Dialog
79. Syntax Highlighting in Module Properties Dialog
80. Autocompletion for Translator Operators
81. Parameters in Illegal States
82. Metadata Parameter
83. Invalid Source Port Link Properties
84. Invalid Destination Port Link Properties
85. Creating New Simulation Sources and Probes
86. Simulation Sources Are Gray Image Frames, Simulation Probes Are Green Image Frames
87. Simulation Source Viewer
88. Viewing Options
89. Pixel Values
90. Zooming in the Magnifier
91. Thumbnail Display in Source
92. Highlighted Image Section Used for Simulation
93. sim[x] Indicates the Image that Is Simulated in a Sequence
94. Crosshair Cursors in Display Window and Magnifier
95. Pixel Values
96. Image Dimensions
97. Exceeded Image Dimensions
98. Bit Widths of Image and Link
99. Defining Offset for Image Bits to Use
100. Display Properties for 4-bit Image
101. Defining Offset for Link Bits to Use
102. Display Alignment
103. Pixel Merge
104. Merging Factor = 1, Image Properties Do Not Fit Link Properties
105. Merging Factor = 2, Properties of Merged Image Fit Link Properties
106. Simulation Window
107. Changing Source and Probe Display
108. Non-connected Simulation Modules
109. Simulation Settings
110. Second Simulation Step
111. Third Simulation Step
112. Successful Simulation
113. Pixel Values Probe
114. Display of Undefined Image Areas
115. Empty Image Symbol
116. Link View
117. Line Profile View
118. Line Histogram View
119. Image Histogram View
120. Save Options Dialog
121. File Format Options for Saving
122. Setting the Splitting Factor in the Save Options Dialog
123. Dialog window for Path Settings
124. Dialog window for Simulation Settings
125. Example: If you always create applets for a Win64 system, you can set this operating system platform here as the default platform
126. Example: Win64 will be suggested by the program when you create a new applet design
127. Dialog window for Diagram Settings
128. Dialog window for Global Build Settings
129. Dialog window for common settings
130. Target Runtime Project Setting
131. Editing the Design Properties
132. Diagram Layout Settings
133. Project Info Window
134. Detailed Information on FPGA Resource Estimation
135. Context Menu FPGA Resources
136. FPGA Resource Usage of Individual Module
137. Device Resource Allocation Window
138. Grayed-out resource CameraControl
139. Device Resource Conflict
140. Auto Correction of Device Resource Conflicts
141. DRC Level 1 Error
142. Detected Xilinx tools
143. Selection of Hardware Platform
144. Build Settings Window
145. Vivado Supported by Target Hardware Design
146. Vivado not Supported by Target Hardware Design
147. Parameter Set Example: Developing for microEnable 5 or LightBridge
148. Defaut: All Build Flow Steps Activated
149. Subsequent Build Steps Deactivated
150. Keeping Build Files of the Individual Build Steps
151. Keeping Build Files of the Individual Build Steps
152. Command Mode Options
153. Command Mode "Use platform default value"
154. Command Mode "Append to platform default value"
155. Command Mode "Overwrite platform default value"
156. Handling Options
157. Selecting the Build Configuration for Applet Build
158. Target Runtime Selection during Applet Build
159. Build Setting for imaFlex CXP-12 Quad and imaFlex CXP-12 Penta
160. Repacking Hardware Applet Files Window
161. Fullfilled Repacking Preconditions
162. Selecting Target Operating System
163. Display of Specified Repacking Settings
164. Message after Successful Repacking
165. Selecting the Storing Location for the SDK Example
166. Script Collection in the VisualApplets program window
167. Exporting a Design
168. Importing a Design
169. User Libraries with Elements in the Library Panel
170. Saving a Hierarchical Box as a User Library Element
171. Adding documentation, version information, short description, and/or individual GUI Icon
172. Providing a password for a library element
173. Tooltip Information on User Library Element
174. Display of Your Library Element in Design
175. Saving New User Library Element
176. Adding documentation, version information, short description, and/or individual GUI Icon
177. Providing a password for a library element
178. Tooltip Information on User Library Element
179.
180. Protecting a user library element
181. Entering password for protected user library element
182. Opening the User Library Editor
183. Replacement of Instances
184. Target Hardware Porting
185. Error message in case an operator is not applicable for new hardware platform
186. Graphical Programming of Image Processing Applications on FPGAs
187. Once-Only Integration Process for new Hardware Platform
188. FPGA Design and IP Core Content as Building Blocks for Bitstream Generation
189. VisualApplets Program Window with Image Processing Design
190. Example for a Simple Image Acquisition Applet with Interface-Requiring Operators
191. Concept of VA IP Core Interfaces
192. Ports of the Register Interface
193. Example IP Core as specified for Zynq Platform
194. Port Layout for Image Input Interface
195. Waveform Illustrating the Protocol on an Image Input Port
196. Example of eVA IP Core
197. Port Layout for Image Output Interface
198. Waveform Illustrating the Protocol on an Image Output Port
199. Example of eVA IP Core
200. Port Layout for Memory Interface Where X Is the Index of the Interface Port
201. Waveform Illustrating the Memory Interface Protocol
202. Example of VA IP Core
203. Example Test Bench for IP Core with 1 ImgIn Interface, 1 ImgOut Interface, 1 Memory Interface, 1 GPI, 1 GPO, and Slave Interface
204. Circuit for Monitoring the Input Data Rate
205. Control Hierarchical Box
206. VisualApplets Main Window
207. New Project window
208. Operator Documentation in VisualApplets
209. Example Design Implementation Sobel_Filter.va
210. Link Properties
211. Static and Dynamic Operator Parameters
212. Design Rule Check 1 and 2 for the Example Design Sobel_Filter.va
213. FPGA Resource Estimation
214. Build Hardware Applet Dialog
215. Firmware Partitions Displayed in microDiagnostics
216. Parameter Tree and Image Acquisition Window in microDisplay
217. Generated SDK Project Files
218. Properties of Operator CameraGrayAreaBase
219. Changed the Link Bit Width of the Camera Operator
220. Bit Width Cannot be Changed at Buffer Module Output Link
221. Illegal Condition after Link Property Change
222. DRC Error Messages Invalid Parameters
223. Red Parameters show Illegal Condition
224. ConvertPixelFormat Operator Added for 16Bit Output
225. ShiftLeft Operator Added for 16Bit Output
226. Block Diagram of Threshold Binarization Design with Monitoring
227. Use of the Binarization Applet in microDisplay
228. VisualApplets design to switch between two cameras
229. Deadlock Configurations using InsertImage
230. Line Duplication
231. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
232. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
233. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Medium Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
234. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on LightBridge VCL, marathon VCL and ironman VCL
235. Basic Acquisition Design for marathon VCL, LightBridge VCL and ironman VCL Frame Grabber for Camera Link Area Scan Cameras in Full Configuration Mode
236. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
237. Basic Acquisition for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode on the LightBridge VCL, marathon VCL and ironman VCL
238. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
239. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
240. Basic Acquisition Design for marathon, LightBridge and ironman Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
241. Basic Acquisition for marathon, LightBridge and ironman Frame Grabber for Camera Link Line Scan Cameras in Full Configuration Mode
242. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6GBit/s Mode with Link Aggregation 1 on the ironman Frame Grabber
243. Basic Acquisition for RGB CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 2 on the ironman Frame Grabber
244. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
245. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the marathon Frame Grabber
246. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 GBit/s Mode with Link Aggregation 1 on the ironman Frame Grabber
247. Basic Acquisition for RGB CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 2 on the ironman Frame Grabber
248. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
249. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the ironman Frame Grabber
250. Basic Acquisition for One Grayscale CoaxPress Area Scan Camera with Link Aggregation 4 on the imaFlex Frame Grabber
251. Basic Acquisition for Four CoaXPress12 Single Link Area Scan Cameras
252. Basic Acquisition Example for Multiple Bit Widths on imaFlex Platform
253. Basic Acquisition Example for Color Format Support on imaFlex Platform
254. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras on the imaFlex Frame Grabber
255. Artificial test image
256. Straight edge
257. Diagonal edge
258. Curved edge
259. Periodic structure
260. Bayer pattern
261. Basic design structure
262. Content of NearestNeighbour
263. Basic design structure
264. Content of HierarchicalBox Laplace
265. Content of HierarchicalBox SortToComponents
266. Basic design structure
267. Interpolation step 1 of the Bayer demosaicing process
268. Content of ColourInterpolation
269. Content of the HierarchicalBox BlueAndRed
270. Original color image
271. Image demosaiced with the algorithm of Laroche et al. [Lar94]
272. Image demosaiced with an bilinear $\text{[math]}$ algorithm
273. Content of ColourInterpolation for the modified Laroche filter.
274. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByGreen_GreenFollowedByBlue/Red
275. Basic design structure of "BilinearBayer_RG_GB.va"
276. Content of HierarchicalBox DeBayer
277. Content of HierarchicalBox DeBayerEnhancedRAW
278. Kernel components created in HierarchicalBox MakeKernel
279. Content of HierarchicalBox DeBayerRAW
280. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByBlue/Red_GreenFollowedByGreen
281. Basic design structure of "BilinearBayer_RB_GG.va"
282. Content of HierarchicalBox DeBayer
283. Content of HierarchicalBox DeBayerEnhanced
284. Kernel components selected in HierarchicalBox DeBayerEnhanced by operator SelectSubKernel3x2
285. Content of HierarchicalBox DeBayerFast
286. Pre-Sorting of Color Components
287. Simulation Result of Pre-Sorted Color Components
288. Parameter Setting for XOffset of the ImageBufferMultiRoI Operator
289. Pre-Sorting for Color Separation by collecting eight successive pixel of the same component.
290. Color Separation with FrameBufferRandomRead
291. Address Generator for FrameBufferRandomRead Input
292. Top level design structure
293. Basic implementation of grayscale JPEG compression using operator JPEG_Encoder
294. Top level design structure
295. Basic implementation of color JPEG compression using user library elements
296. Basic implementation of grayscale JPEG compression using operator JPEG_Encoder_Gray
297. Basic design structure
298. Content of box JPEGBlockSorter8x8
299. Rearangement of Pixel in JPEGBlockSorter8x8
300. Content of SplitImage box
301. Content of the RemoveFillByte box
302. Content of the RestartMarker box
303. Basic design structure
304. Block Diagram of the applet Hardware Test
305. Hardware Test Process0
306. Hardware Test Process1
307. Applet Hardware Test use of Parameter Translates and References in microDisplay
308. Applet Hardware Test Implementation for RAM Test, DMA Perfomance Test and Camera Acquisition
309. Use of FloatParamTranslator to Convert from Frames per Second to Ticks
310. Use of IntParamTranslator for easy Setting of the Width and Height in the Applet
311. Basic design structure of the VA design "TriggerAndImageStatistics.va"
312. Content of HierarchicalBox TriggerAnalysis
313. Content of HierarchicalBox CameraLink_InputStatistics
314. Content of HierarchicalBox Trigger_Statistics
315. Content of HierarchicalBox DelayAnalysis
316. Content of HierarchicalBox ImageAnalysis
317. Sinewave
318. FFT Result for mE5-VD8-CL. At position 32 the real part value is -43 and imaginary part is -67108738.
319. Basic design structure of the VA design "GeometricTransformation_FrameBufferRandomRead.va"
320. Content of HierarchicalBox"GeometricTransformation"
321. Content of HierarchicalBox CoordinateTransformation
322. Content of HierarchicalBox OutputImage
323. Content of HierarchicalBox InverseTransformation
324. Source image [Ope16a]
325. Rotated and translated target image
326. Basic design structure of the VA design "GeometricTransformation_ImageMoments.va"
327. Content of the HierarchicalBox GeometricTransformation
328. Content of HierarchicalBox CoordinateTransformation
329. Content of HierarchicalBox InverseTransformation
330. Content of HierarchicalBox GeometricTransformation
331. Source image (dimension: 640x240 pixels)
332. Position and orientation corrected target image (dimension: 256x128 pixels)
333. Example: 8 Pixels are stored in one DRAM cell
334. Content of HierarchicalBox FrameBufferRandomRead_Par8
335. Basic design structure of the VA design "GeometricTransformation_DistortionCorrection.va"
336. Content of HierarchicalBox CoordinateTransformation
337. Content of HierarchicalBox KeystoneCorrection
338. Content of HierarchicalBox DistortionCorrection
339. Content of HierarchicalBox DistortionCoefficient
340. Example Source Image [Ope16a]
341. Distortion and Keystone corrected target image
342. Rotated, distortion and Keystone corrected target image
343. Basic design structure of the VA design "DistortionCorrection.va"
344. Content of HierarchicalBox DistortionCorrection
345. Content of HierarchicalBox InverseCorrection
346. Basic design structure
347. Content of ImageMoments
348. Content of the HierarchicalBox orientation_theta
349. Content of the HierarchicalBox eccentricity
350. Skew of a scanned object resulting from camera misalignment
351. Basic design structure
352. Content of HierarchicalBox LineShear
353. Content of HierarchicalBox ExtractInteger
354. Content of HierarchicalBox Select
355. Content of HierarchicalBox TransformedYCoordinate
356. Shift corrected image
357. Basic design structure for scaling a line camera image
358. Components of Transformation
359. Components of WordToRead
360. Components of PixelPicker
361. Content of Pick_0
362. Components of Interpolation
363. Basic design structure for "TapSorting_2XE_1Y.va"
364. Basic design structure of "TapSorting_2X_2Y.va"
365. Content of the HierarchicalBox Address in "TapSorting_2X_2Y.va"
366. Basic design structure of "TapSorting_8X_1Y.va"
367. Content of the HierarchicalBox Sorting_8X_1Y
368. Content of the HierarchicalBox Address in "TapSorting_8X_1Y.va"
369. Basic design structure
370. Content of box Trigger
371. Content of box HDR
372. Content of component Red in Image1
373. Content of box Red under HDR
374. Content of box LDR in the designs "HDR_CRC_Bayer.va" and "HDR_CRC_Color.va"
375. Content of box LDR in the design "HDR_CRC_Gray.va"
376. Basic design structure
377. Content of box HDR
378. Content of Red in box Image1
379. Content of Red in box HDR
380. Basic design structure of "ExposureFusion.va"
381. Content of HierarchicalBox ExposureFusion
382. Content of HierarchicalBox ImageComposition
383. Content of HierarchicalBox Weight
384. Content of HierarchicalBox Red in box Weight
385. Content of HierarchicalBox Red in box ImageComposition
386. Example input images with different exposure times
387. Result image of the 5 example input images after exposure fusion
388. Basic design structure
389. Content of HierarchicalBox DepthFromFocus
390. Content of HierarchicalBox CompareContrast
391. Content of HierarchicalBox SelectDepthIndex
392. Content of HierarchicalBox SelectPixelValue
393. Content of HierarchicalBox LastImageOfSequenceOnly
394. Basic Design structure of the VA designs "HOG_9Bins_Histogram.va","HOG_9Bins_HistogramMax.va" and "HOG_4Bins_HistogramMax.va"
395. Content of HierarchicalBiox HOG
396. Content of HierarchicalBox GradientFilter
397. Content of HierarchicalBox MagnitudeOrientation
398. Content of HierarchicalBox Histogram
399. Content of HierarchicalBox Bin1
400. Content of HierarchicalBox ConcatenateWithNeighbors
401. Content of HierarchicalBox GetHistogramMax
402. Basic design structure of the VA design "PrintInspection_Blob.va"
403. Content of the HierarchicalBox FindPatterns
404. Content of the HierarchicalBox ExtractCandidates
405. Content of the HierarchicalBox DetermingCOGTemplates
406. Content of the HierarchicalBox TemplateMatching
407. Content of the HierarchicalBox COG_Angle
408. Basic design structure of the VA design "PrintInspection_ImageMoments.va"
409. Basic design structure of "NormalizedCrossCorrelation.va"
410. Test image "PCB.tif"
411. Content of HierarchicalBox NCC
412. Content of HierarchicalBox Division
413. result image with "1" at object positions (zoomed view)
414. Objects Visualized by Colored Boxes
415. 4-Connected Neighborhood
416. 8-Connected Neighborhood
417. Pixels allocated to objects in a 4-connected neighborhood (left) and an 8-connected neighborhood (right). All colored pixels represent foreground pixels where their allocation to objects is visualized by differing colors.
418. 4-Connected Neighborhood: Contour Orthogonal = 30, Diagonal = 0
419. 8-Connected Neighborhood: Contour Orthogonal = 14, Diagonal = 8
420. Calculation of the perimeter using an 8-connected neighborhood (left) and a 4-connected neighborhood (right)
421. Impact of Y-Coordinate Reset
422. Behavior of Overflow Events
423. Flush Behavior of the BlobDetector1D Operator
424. Error Flag in the Simulation Probe Viewer
425. Error Flag in the Simulation Probe Viewer
426. Behavior of the Blob Analysis 1D Operator
427. Synchronization of the Blob 1D Operator in a VisualApplets Network
428. Blob 1D Timing - Generation of New Frames
429. Blob 1D Timing - Suppression of Empty Frames
430. Blob 1D Timing - Constant Flush
431. Blob 1D Timing - Discarding of Objects
432. Simulation Scenario 1 - Flush and Y0 Relation
433. Simulation Scenario 2 - Flush Pixel Position
434. Simulation Scenario 3 - Discarded Flush Pixel at End of Frame
435. Simulation Scenario 4 - Multiple Blobs
436. Formula for calculating the minimum input image width
437. Overflow Event Data
438. This configuration is equivalent to a simpler CxpCamera operator with only O output and no meta data.
439. This configuration is equivalent to a simpler CxpCamera operator with port O and MetaDataO selected.
440. In this configuration only the tap 0 is output with its metadata. For the tap 1 only the metadata is output. This configuration can be useful for debugging a camera/frame grabber combination.
441. In this configuration the operator provides both camera taps as 2 separate data streams on its Tap0 and Tap1 ports. However, no metadata information is output.
442. In this configuration the operator provides both camera taps as 2 separate streams on its Tap0 and Tap1 ports. The operator provides also the meta information for the Tap0 port. This configuration might be meaningful for symmetrical camera tap configurations, where the CXP header is in most parts identical for both taps except for the TapG Code fields.
443. This is the maximal configuration of the operator, where for each tap an own output is presented together with its own metadata.
444. RAM architecture

List of Tables

1. Shortcut List for Main Program Window
2. Shortcut List for Simulation Viewer
3. Command Line Options and According Arguments
4. Operator Types
5. Availability of Autocompletion and Syntax Highlighting
6. List of Device Resources
7. Operator/Info
8. Operator/IO
9. Operator/Properties
10. Operator/ImgIn
11. Operator/ImgOut
12. Operator/RegIn
13. Operator/RegOut
14. Operator/Mem
15. Operator/Core
16. List of Basic Acquisition Examples
17. List of Bayer Demosaicing Examples
18. Overview of Color Separation Examples
19. Design Versions for Grayscale JPEG Encoding
20. Design Versions for Color JPEG Encoding
21. List of Geometric Transformation Examples
22. Reading Cycles
23. Files and their corresponding lookup tables in Visual Applets
24. Examples of tap geometries
25. Available Libraries
26. Operators of Library Accumulator
27. Operators of Library Arithmetics
28. Operators of Library Base
29. Examples
30. Explanation of pseudo-code
31. Examples
32. Examples
33. Operators of Library Blob
34. Explanation of Blob Error Flags
35. Explanation of Blob Error Flags
36. Explanation of Blob Error Flags
37. Explanation of Blob Error Flags
38. Operators of Library Color
39. Operators of Library Compression
40. Operators of Library Debugging
41. Operators of Library Filter
42. Operators of Library Logic
43. Memory Types of Operators in the Library Memory
44. Individual Latencies of the Operators in Library Memory
45. Operators of Library Memory
46. Data types supported by reference operators
47. Operators of Library Parameters
48. Basic operations
49. Functions
50. Basic operations
51. Functions
52. Basic operations
53. Functions
54. Operators of Library Hardware Platform
55. Mapping VA notation and CL Specification Version 2.1
56. Mapping VA notation and CL Specification Version 2.1
57. Mapping VA notation and CL Specification Version 2.1
58.
59.
60.
61.
62. Operators of Library Prototype
63. Operators of Library Signal
64. Operators of Library Synchronization
65. Operators of Library Transformation
66. Hardware Configuration imaFlex CXP-12 Quad and imaFlex CXP-12 Penta
67. Hardware Configuration LightBridge and microEnable 5 marathon
68. Hardware Configuration microEnable 5 ironman
69. List of Device Resources imaFlex CXP-12 Quad and imaFlex CXP-12 Penta
70. List of Device Resources LightBridge and microEnable 5 marathon
71. List of Device Resources microEnable 5 ironman

List of Equations

1. Overlay Blend
2. Optimized Overlay Blend for FPGA Implementation

Contents
Search

loading table of contents...

Search Highlighter (On/Off)