Table of Contents
- User Manual
- Tutorial and Examples
-
- Introduction
- Hardware Applet: From Idea to Application
- Basic Design Theory
- Basic Acquisition Designs for Varying Camera Types and Hardware Platforms
- Processing Examples
-
- Artificial Image Source
- Binarization
- Blob Detection
- Color
- Compression
- Co-Processor
- Debugging and Test
- Difference Images
- Fast Fourier Transform
- Filter
- Signals And Events
- Geometry
- High Dynamic Range and Image Composition
- Laser Detection
- Lookup Table
- Loop
- Multiple Regions Of Interest
- Object Features
- Shading Correction
- Trigger
- Operator Examples
-
- Functional Example for Specific Operators of Library Accumulator and Library Logic
- Functional Example for Specific Operators of Library Synchronization: Dynamic Append and Cut
- Functional Example for Specific Operators of Library Memory and Library Signal
- Functional Example for Specific Operators of Library Memory and Library Signal
- Functional Example for Specific Operators of Library Signal
- Functional Example for Specific Operators of Library Synchronization, Base and Filter
- Functional Example for Specific Operators of Library Arithmentics: Trigonometric Functions
- Functional Example for Specific Operators of Library Color, Base and Memory
- Functional Example for Specific Operators of Library Signal, Logic, Filter and Parameters
- Parameter Library Examples
- Using Applets During Runtime
- Operator Reference
-
- Introduction
- Library Overview
- Library Accumulator
- Library Arithmetics
- Library Base
-
- BRANCH
- CastBitWidth
- CastColorSpace
- CastKernel
- CastParallel
- CastType
- CONST
- ConvertPixelFormat
- Coordinate_X
- Coordinate_Y
- Dummy
- DynamicROI
- EventToHost
- EventDataToHost
- ExpandToKernel
- ExpandToParallel
- GetStatus
- HierarchicalBox
- ImageNumber
- KernelRemap
- MergeComponents
- MergeKernel
- MergeParallel
- MergePixel
- NOP
- PARALLELdn
- PARALLELup
- PseudoRandomNumberGen
- SampleDn
- SampleUp
- SelectBitField
- SelectComponent
- SelectFromParallel
- SelectROI
- SelectSubKernel
- SetDimension
- SplitComponents
- SplitKernel
- SplitParallel
- Trash
- Library Blob
- Library Color
- Library Compression
- Library Debugging
- Library Filter
- Library Logic
- Library Memory
-
- CoefficientBuffer
- CoefficientBufferMultiRoi (imaFlex)
- FrameBufferMultiRoi (imaFlex)
- FrameBufferMultiRoiDyn
- FrameBufferRandomRead
- FrameBufferRandomRead (imaFlex)
- FrameMemory
- FrameMemoryRandomRd
- ImageBuffer
- ImageBufferMultiRoI
- ImageBufferMultiRoIDyn
- ImageBufferSC
- ImageFifo
- KneeLUT
- LineBuffer (imaFlex)
- LineMemory
- LineMemoryRandomRd
- LUT
- RamLUT
- RamLUT (imaFlex)
- ROM
- Library Parameters
-
- EnumParamReference
- EnumParamTranslator
- EnumVariable
- FloatFieldParamReference
- FloatParamReference
- FloatParamTranslator
- FloatVariable
- IntFieldParamReference
- IntParamReference
- IntParamTranslator
- IntVariable
- IntFieldVariable
- LinkProperties
- LinkParamTranslator
- StringParamReference
- ResourceReference
- IntParamSelector
- FloatParamSelector
- Library Hardware Platform
-
- AppletProperties
- BaseGrayCamera
- BaseRgbCamera
- BoardStatus
- CameraControl
- CLHSDualCamera
- CLHSPulseIn
- CLHSPulseOut
- CLHSSingleCamera
- CoFCamera
- CoFPortStatus
- CoFRxTrigger
- CoFTxTrigger
- CxpAcquisitionStatus
- CxpCamera
- CxpCameraMultiTap
- CXPDualCamera
- CXPQuadCamera
- CXPSingleCamera
- CxpPortStatus
- CxpRxTrigger
- CxpTxTrigger
- DFLed
- DFRxData
- DFRxMeta
- DFTxData
- DFTxMeta
- DmaFromPC
- DmaToPC
- FullGrayCamera
- FullRgbCamera
- GPI
- GPO
- LED
- MediumGrayCamera
- MediumRgbCamera
- Library Prototype
- Library Signal
-
- DelayToSignal
- Downscale
- EventToSignal
- FrameEndToSignal
- FrameStartToSignal
- Generate
- GetSignalStatus
- Gnd
- LimitSignalWidth
- LineEndToSignal
- LineStartToSignal
- PeriodToSignal
- PixelToSignal
- Polarity
- PulseCounter
- RsFlipFlop
- RxSignalLink
- Select
- SetSignalStatus
- ShaftEncoder
- ShaftEncoderCompensate
- SignalDebounce
- SignalDelay
- SignalEdge
- SignalGate
- SignalToDelay
- SignalToPeriod
- SignalToPixel
- SignalToWidth
- SignalWidth
- SyncSignal
- TxSignalLink
- Vcc
- WidthToSignal
- Library Synchronization
-
- AppendImage
- AppendImageDyn
- AppendLine
- AppendLineDyn
- CutImage
- CutLine
- CreateBlankImage
- ExpandLine
- ExpandPixel
- ImageValve
- InsertImage
- InsertLine
- InsertPixel
- IsFirstPixel
- IsLastPixel
- PixelReplicator
- PixelToImage
- RemoveImage
- RemoveLine
- RemovePixel
- ReSyncToLine
- RxImageLink
- SourceSelector
- SplitImage
- SplitLine
- SYNC
- TxImageLink
- Overflow
- Library Transformation
- Device Resources
- Glossary
- Bibliography
- Index
List of Figures
- 1. VisualApplets - From Idea to Image Processor in 15 Minutes
- 2. VisualApplets – Awarded Software Environment
- 3. Main Program Window
- 4. Operator not available for currently selected target hardware platform
- 5. The Information Panel
- 6. Project Info
- 7. Module Search
- 8. Module Search
- 9. Parameter Info
- 10. DRC Log Information
- 11. Build Log Information
- 12. Example: Displaying Information on the MergeKernel Operator
- 13. Library Panel with Operator Library on Display
- 14. Library Panel with Operator Library on Display
- 15. Undock via Context Menu
- 16. Undock via button
- 17. Re-docking Floating Windows
- 18. Opening the Split View
- 19. Split View
- 20. Configuring the number of displayed recent designs
- 21. Applet with Four Processes
- 22. Creating a New Process
- 23. VisualApplets Main Window
- 24. Start of a New Project
- 25. Dragging Operators from Libraries into the Design Window
- 26. Module Properties
- 27. Successful DRC
- 28. Build Settings for microEnable 5 / Xilinx Vivado
- 29. Simple VisualApplets Design
- 30. The Design Workflow
- 31. FPGA vs. CU Transfer/Processing Performance
- 32. Transferring and Processing Images in VisualApplets Data Pipeline
- 33. Simple VisualApplets Design
- 34. Parallelism for Clock Frequency of 125 MHz
- 35. Pixel Order
- 36. Model of a 2D Image Protocol
- 37. Model of a 1D Image Protocol
- 38. Model of an 0D Image Protocol
- 39. Start of a new Project
- 40. Edit Project Details
- 41. Menu Design, menu item Change FPGA Clock
- 42. Slider and spin box for selecting FPGA clock frequency
- 43. Operator Libraries
- 44. Error message in case an operator is not applicable for another hardware platform
- 45. Example of a Hierarchical Box
- 46. Window tabs of the design window
- 47. Highlighting a Port
- 48. Highlighting a Port
- 49. Entering a port name
- 50. Renamed ports of a hierarchical box
- 51. Highlighting a port
- 52. Reordered input ports of a hierarchical box
- 53. O-Type Network
- 54. Failing O-Type Network
- 55. Display of not correctly synchronized data flow in VisualApplets 2.2 and higher
- 56. M-type and O-type Network
- 57. M-type Operator with One Synchronous Input Group
- 58. M-type Operator with Asynchronous Inputs
- 59. Synchronization of Independent Sources
- 60. Deadlock at SYNC, figure a
- 61. Deadlock at SYNC, figure b
- 62. Fixed Deadlock
- 63. Deadlock Avoided
- 64. Bandwidth Limitation
- 65. Bandwidth Limitation Compensated
- 66. Infinite Source Connection Error
- 67. Infinite Source Connection OK
- 68. Infinite source conversion module (Buffer1) connected to a non-infinite source
- 69. O-type module with signal link inputs, sourced by different M-type modules
- 70. The Parameter Info View
- 71. Parameter Info
- 72. Module Properties Dialog
- 73. Field Parameter Edit Window
- 74. Function Dialog to Edit Field Parameters
- 75. Disabled Parameters
- 76. Autocompletion for Reference Parameters
- 77. Autocompletion in "Enter data for <operator>/<parameter> Dialog
- 78. Syntax Highlighting in "Enter data for <operator>/<parameter> Dialog
- 79. Syntax Highlighting in Module Properties Dialog
- 80. Autocompletion for Translator Operators
- 81. Parameters in Illegal States
- 82. Metadata Parameter
- 83. Invalid Source Port Link Properties
- 84. Invalid Destination Port Link Properties
- 85. Creating New Simulation Sources and Probes
- 86. Simulation Sources Are Gray Image Frames, Simulation Probes Are Green Image Frames
- 87.
- 88. Viewing Options
- 89. Pixel Values
- 90. Zooming in the Magnifier
- 91. Thumbnail Display in Source
- 92. Highlighted Image Section Used for Simulation
- 93. sim[x] Indicates the Image that Is Simulated in a Sequence
- 94. Crosshair Cursors in Display Window and Magnifier
- 95. Pixel Values
- 96. Image Dimensions
- 97. Exceeded Image Dimensions
- 98. Bit Widths of Image and Link
- 99. Defining Offset for Image Bits to Use
- 100. Display Properties for 4-bit Image
- 101. Defining Offset for Link Bits to Use
- 102. Display Alignment
- 103. Pixel Merge
- 104. Merging Factor = 1, Image Properties Do Not Fit Link Properties
- 105. Merging Factor = 2, Properties of Merged Image Fit Link Properties
- 106. Simulation Window
- 107. Changing Source and Probe Display
- 108. Non-connected Simulation Modules
- 109. Simulation Settings
- 110. Second Simulation Step
- 111. Third Simulation Step
- 112. Successful Simulation
- 113. Pixel Values Probe
- 114. Display of Undefined Image Areas
- 115. Empty Image Symbol
- 116. Link View
- 117. Line Profile View
- 118. Line Histogram View
- 119. Image Histogram View
- 120. Save Options Dialog
- 121. File Format Options for Saving
- 122. Setting the Splitting Factor in the Save Options Dialog
- 123. Dialog window for Path Settings
- 124. Dialog window for Simulation Settings
- 125. Example: If you always create applets for a Win64 system, you can set this operating system platform here as the default platform
- 126. Example: Win64 will be suggested by the program when you create a new applet design
- 127. Dialog window for Diagram Settings
- 128. Dialog window for Global Build Settings
- 129. Dialog window for common settings
- 130. Target Runtime Project Setting
- 131. Editing the Design Properties
- 132. Diagram Layout Settings
- 133. Project Info Window
- 134. Detailed Information on FPGA Resource Estimation
- 135. Context Menu FPGA Resources
- 136. FPGA Resource Usage of Individual Module
- 137. Device Resource Allocation Window
- 138. Grayed-out resource CameraControl
- 139. Device Resource Conflict
- 140. Auto Correction of Device Resource Conflicts
- 141. DRC Level 1 Error
- 142. Detected Xilinx tools
- 143. Selection of Hardware Platform
- 144. Build Settings Window
- 145. Vivado Supported by Target Hardware Design
- 146. Vivado not Supported by Target Hardware Design
- 147. Parameter Set Example: Developing for microEnable 5 marathon
- 148. Defaut: All Build Flow Steps Activated
- 149. Subsequent Build Steps Deactivated
- 150. Keeping Build Files of the Individual Build Steps
- 151. Keeping Build Files of the Individual Build Steps
- 152. Command Mode Options
- 153. Command Mode "Use platform default value"
- 154. Command Mode "Append to platform default value"
- 155. Command Mode "Overwrite platform default value"
- 156. Handling Options
- 157. Selecting the Build Configuration for Applet Build
- 158. Target Runtime Selection during Applet Build
- 159. Build Setting for imaFlex CXP-12 Quad and imaFlex CXP-12 Penta
- 160. Repacking Hardware Applet Files Window
- 161. Fullfilled Repacking Preconditions
- 162. Selecting Target Operating System
- 163. Display of Specified Repacking Settings
- 164. Message after Successful Repacking
- 165. Selecting the Storing Location for the SDK Example
- 166. Script Collection in the VisualApplets program window
- 167. Exporting a Design
- 168. Importing a Design
- 169. User Libraries with Elements in the Library Panel
- 170. Saving a Hierarchical Box as a User Library Element
- 171. Adding documentation, version information, short description, and/or individual GUI Icon
- 172. Providing a password for a library element
- 173. Tooltip Information on User Library Element
- 174. Display of Your Library Element in Design
- 175. Saving New User Library Element
- 176. Adding documentation, version information, short description, and/or individual GUI Icon
- 177. Providing a password for a library element
- 178. Tooltip Information on User Library Element
- 179.
- 180. Protecting a user library element
- 181. Entering password for protected user library element
- 182. Opening the User Library Editor
- 183. Replacement of Instances
- 184. Target Hardware Porting
- 185. Error message in case an operator is not applicable for new hardware platform
- 186. VisualApplets Main Window
- 187. New Project window
- 188. Operator Documentation in VisualApplets
- 189. Example Design Implementation
Sobel_Filter.va - 190. Link Properties
- 191. Static and Dynamic Operator Parameters
- 192. Design Rule Check 1 and 2 for the Example Design
Sobel_Filter.va - 193. FPGA Resource Estimation
- 194. Build Hardware Applet Dialog
- 195. Firmware Partitions Displayed in microDiagnostics
- 196. Parameter Tree and Image Acquisition Window in microDisplay
- 197. Generated SDK Project Files
- 198. Properties of Operator CameraGrayAreaBase
- 199. Changed the Link Bit Width of the Camera Operator
- 200. Bit Width Cannot be Changed at Buffer Module Output Link
- 201. Illegal Condition after Link Property Change
- 202. DRC Error Messages Invalid Parameters
- 203. Red Parameters show Illegal Condition
- 204. ConvertPixelFormat Operator Added for 16Bit Output
- 205. ShiftLeft Operator Added for 16Bit Output
- 206. Block Diagram of Threshold Binarization Design with Monitoring
- 207. Use of the Binarization Applet in microDisplay
- 208. VisualApplets design to switch between two cameras
- 209. Deadlock Configurations using InsertImage
- 210. Line Duplication
- 211. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Base Configuration Mode on marathon VCL
- 212. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on marathon VCL
- 213. Basic Acquisition for Grayscale Camera Link Area Scan Cameras in Medium Configuration Mode on marathon VCL
- 214. Basic Acquisition for RGB Camera Link Area Scan Cameras in Base Configuration Mode on marathon VCL
- 215. Basic Acquisition Design for marathon VCL Frame Grabber for Camera Link Area Scan Cameras in Full Configuration Mode
- 216. Basic Acquisition Design for marathon Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
- 217. Basic Acquisition Design for marathon Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
- 218. Basic Acquisition Design for marathon Frame Grabber for Grayscale Camera Link Line Scan Cameras in Base Configuration Mode
- 219. Basic Acquisition Design for marathon Frame Grabber for RGB Camera Link Line Scan Cameras in Base Configuration Mode
- 220. Basic Acquisition for marathon Frame Grabber for Camera Link Line Scan Cameras in Full Configuration Mode
- 221. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6GBit/s Mode with Link Aggregation 1
- 222. Basic Acquisition for RGB CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 2
- 223. Basic Acquisition for Grayscale CoaxPress Area Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4 on the marathon Frame Grabber
- 224. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 GBit/s Mode with Link Aggregation 1
- 225. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras in 6 Gbit/s Mode with Link Aggregation 4
- 226. Basic Acquisition for One Grayscale CoaxPress Area Scan Camera with Link Aggregation 4 on the imaFlex Frame Grabber
- 227. Basic Acquisition for Four CoaXPress12 Single Link Area Scan Cameras
- 228. Basic Acquisition Example for Multiple Bit Widths on imaFlex Platform
- 229. Basic Acquisition Example for Color Format Support on imaFlex Platform
- 230. Basic Acquisition for Grayscale CoaxPress Line Scan Cameras on the imaFlex Frame Grabber
- 231. Daisy-chained Frame Grabbers (Data Forwarding)
- 232. Artificial test image
- 233. Straight edge
- 234. Diagonal edge
- 235. Curved edge
- 236. Periodic structure
- 237. Bayer pattern
- 238. Basic design structure
- 239. Content of NearestNeighbour
- 240. Basic design structure
- 241. Content of HierarchicalBox Laplace
- 242. Content of HierarchicalBox SortToComponents
- 243. Basic design structure
- 244. Interpolation step 1 of the Bayer demosaicing process
- 245. Content of ColourInterpolation
- 246. Content of the HierarchicalBox BlueAndRed
- 247. Original color image
- 248. Image demosaiced with the algorithm of Laroche et al. [Lar94]
- 249. Image demosaiced with an bilinear
algorithm - 250. Content of ColourInterpolation for the modified Laroche filter.
- 251. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByGreen_GreenFollowedByBlue/Red
- 252. Basic design structure of "BilinearBayer_RG_GB.va"
- 253. Content of HierarchicalBox DeBayer
- 254. Content of HierarchicalBox DeBayerEnhancedRAW
- 255. Kernel components created in HierarchicalBox MakeKernel
- 256. Content of HierarchicalBox DeBayerRAW
- 257. Sensor layout of a bilinear line scan camera with color pattern Red/BlueFollowedByBlue/Red_GreenFollowedByGreen
- 258. Basic design structure of "BilinearBayer_RB_GG.va"
- 259. Content of HierarchicalBox DeBayer
- 260. Content of HierarchicalBox DeBayerEnhanced
- 261. Kernel components selected in HierarchicalBox DeBayerEnhanced by operator SelectSubKernel3x2
- 262. Content of HierarchicalBox DeBayerFast
- 263. Pre-Sorting of Color Components
- 264. Simulation Result of Pre-Sorted Color Components
- 265. Parameter Setting for XOffset of the ImageBufferMultiRoI Operator
- 266. Pre-Sorting for Color Separation by collecting eight successive pixel of the same component.
- 267. Color Separation with FrameBufferRandomRead
- 268. Address Generator for FrameBufferRandomRead Input
- 269. Top level design structure
- 270. Basic implementation of grayscale JPEG compression using operator JPEG_Encoder
- 271. Top level design structure
- 272. Basic implementation of color JPEG compression using user library elements
- 273. Basic implementation of grayscale JPEG compression using operator JPEG_Encoder_Gray
- 274. Basic design structure
- 275. Content of box JPEGBlockSorter8x8
- 276. Rearangement of Pixel in JPEGBlockSorter8x8
- 277. Content of SplitImage box
- 278. Content of the RemoveFillByte box
- 279. Content of the RestartMarker box
- 280. Basic design structure
- 281. Block Diagram of the applet Hardware Test
- 282. Hardware Test Process0
- 283. Hardware Test Process1
- 284. Applet Hardware Test use of Parameter Translates and References in microDisplay
- 285. Applet Hardware Test Implementation for RAM Test, DMA Perfomance Test and Camera Acquisition
- 286. Use of FloatParamTranslator to Convert from Frames per Second to Ticks
- 287. Use of IntParamTranslator for easy Setting of the Width and Height in the Applet
- 288. Basic design structure of the VA design "TriggerAndImageStatistics.va"
- 289. Content of HierarchicalBox TriggerAnalysis
- 290. Content of HierarchicalBox CameraLink_InputStatistics
- 291. Content of HierarchicalBox Trigger_Statistics
- 292. Content of HierarchicalBox DelayAnalysis
- 293. Content of HierarchicalBox ImageAnalysis
- 294. Sinewave
- 295. Basic design structure of the VA design "GeometricTransformation_FrameBufferRandomRead.va"
- 296. Content of HierarchicalBox"GeometricTransformation"
- 297. Content of HierarchicalBox CoordinateTransformation
- 298. Content of HierarchicalBox OutputImage
- 299. Content of HierarchicalBox InverseTransformation
- 300. Source image [Ope16a]
- 301. Rotated and translated target image
- 302. Basic design structure of the VA design "GeometricTransformation_ImageMoments.va"
- 303. Content of the HierarchicalBox GeometricTransformation
- 304. Content of HierarchicalBox CoordinateTransformation
- 305. Content of HierarchicalBox InverseTransformation
- 306. Content of HierarchicalBox GeometricTransformation
- 307. Source image (dimension: 640x240 pixels)
- 308. Position and orientation corrected target image (dimension: 256x128 pixels)
- 309. Example: 8 Pixels are stored in one DRAM cell
- 310. Content of HierarchicalBox FrameBufferRandomRead_Par8
- 311. Basic design structure of the VA design "GeometricTransformation_DistortionCorrection.va"
- 312. Content of HierarchicalBox CoordinateTransformation
- 313. Content of HierarchicalBox KeystoneCorrection
- 314. Content of HierarchicalBox DistortionCorrection
- 315. Content of HierarchicalBox DistortionCoefficient
- 316. Example Source Image [Ope16a]
- 317. Distortion and Keystone corrected target image
- 318. Rotated, distortion and Keystone corrected target image
- 319. Basic design structure of the VA design "DistortionCorrection.va"
- 320. Content of HierarchicalBox DistortionCorrection
- 321. Content of HierarchicalBox InverseCorrection
- 322. Basic design structure
- 323. Content of ImageMoments
- 324. Content of the HierarchicalBox orientation_theta
- 325. Content of the HierarchicalBox eccentricity
- 326. Skew of a scanned object resulting from camera misalignment
- 327. Basic design structure
- 328. Content of HierarchicalBox LineShear
- 329. Content of HierarchicalBox ExtractInteger
- 330. Content of HierarchicalBox Select
- 331. Content of HierarchicalBox TransformedYCoordinate
- 332. Shift corrected image
- 333. Basic design structure for scaling a line camera image
- 334. Components of Transformation
- 335. Components of WordToRead
- 336. Components of PixelPicker
- 337. Content of Pick_0
- 338. Components of Interpolation
- 339. Basic design structure for "TapSorting_2XE_1Y.va"
- 340. Basic design structure of "TapSorting_2X_2Y.va"
- 341. Content of the HierarchicalBox Address in "TapSorting_2X_2Y.va"
- 342. Basic design structure of "TapSorting_8X_1Y.va"
- 343. Content of the HierarchicalBox Sorting_8X_1Y
- 344. Content of the HierarchicalBox Address in "TapSorting_8X_1Y.va"
- 345. Basic design structure
- 346. Content of box Trigger
- 347. Content of box HDR
- 348. Content of component Red in Image1
- 349. Content of box Red under HDR
- 350. Content of box LDR in the designs "HDR_CRC_Bayer.vad" and "HDR_CRC_Color.vad"
- 351. Content of box LDR in the design "HDR_CRC_Gray.vad"
- 352. Basic design structure
- 353. Content of box HDR
- 354. Content of Red in box Image1
- 355. Content of Red in box HDR
- 356. Basic design structure of "ExposureFusion.vad"
- 357. Content of HierarchicalBox ExposureFusion
- 358. Content of HierarchicalBox ImageComposition
- 359. Content of HierarchicalBox Weight
- 360. Content of HierarchicalBox Red in box Weight
- 361. Content of HierarchicalBox Red in box ImageComposition
- 362. Example input images with different exposure times
- 363. Result image of the 5 example input images after exposure fusion
- 364. Basic design structure
- 365. Content of HierarchicalBox DepthFromFocus
- 366. Content of HierarchicalBox CompareContrast
- 367. Content of HierarchicalBox SelectDepthIndex
- 368. Content of HierarchicalBox SelectPixelValue
- 369. Content of HierarchicalBox LastImageOfSequenceOnly
- 370. Basic Design structure of the VA designs "HOG_9Bins_Histogram.vad","HOG_9Bins_HistogramMax.vad" and "HOG_4Bins_HistogramMax.vad"
- 371. Content of HierarchicalBiox HOG
- 372. Content of HierarchicalBox GradientFilter
- 373. Content of HierarchicalBox MagnitudeOrientation
- 374. Content of HierarchicalBox Histogram
- 375. Content of HierarchicalBox Bin1
- 376. Content of HierarchicalBox ConcatenateWithNeighbors
- 377. Content of HierarchicalBox GetHistogramMax
- 378. Basic design structure of the VA design "PrintInspection_Blob.vad"
- 379. Content of the HierarchicalBox FindPatterns
- 380. Content of the HierarchicalBox ExtractCandidates
- 381. Content of the HierarchicalBox DetermingCOGTemplates
- 382. Content of the HierarchicalBox TemplateMatching
- 383. Content of the HierarchicalBox COG_Angle
- 384. Basic design structure of the VA design "PrintInspection_ImageMoments.vad"
- 385. Basic design structure of "NormalizedCrossCorrelation.vad"
- 386. Test image "PCB.tif"
- 387. Content of HierarchicalBox NCC
- 388. Content of HierarchicalBox Division
- 389. result image with "1" at object positions (zoomed view)
- 390. Objects Visualized by Colored Boxes
- 391. 4-Connected Neighborhood
- 392. 8-Connected Neighborhood
- 393. Pixels allocated to objects in a 4-connected neighborhood (left) and an 8-connected neighborhood (right). All colored pixels represent foreground pixels where their allocation to objects is visualized by differing colors.
- 394. 4-Connected Neighborhood: Contour Orthogonal = 30, Diagonal = 0
- 395. 8-Connected Neighborhood: Contour Orthogonal = 14, Diagonal = 8
- 396. Calculation of the perimeter using an 8-connected neighborhood (left) and a 4-connected neighborhood (right)
- 397. Impact of Y-Coordinate Reset
- 398. Behavior of Overflow Events
- 399. Flush Behavior of the BlobDetector1D Operator
- 400. Error Flag in the Simulation Probe Viewer
- 401. Error Flag in the Simulation Probe Viewer
- 402. Behavior of the Blob Analysis 1D Operator
- 403. Synchronization of the Blob 1D Operator in a VisualApplets Network
- 404. Blob 1D Timing - Generation of New Frames
- 405. Blob 1D Timing - Suppression of Empty Frames
- 406. Blob 1D Timing - Constant Flush
- 407. Blob 1D Timing - Discarding of Objects
- 408. Simulation Scenario 1 - Flush and Y0 Relation
- 409. Simulation Scenario 2 - Flush Pixel Position
- 410. Simulation Scenario 3 - Discarded Flush Pixel at End of Frame
- 411. Simulation Scenario 4 - Multiple Blobs
- 412. Formula for calculating the minimum input image width
- 413. Overflow Event Data
- 414. FPGA Device Resources
- 415. FPGA Device Resources
- 416. FPGA Device Resources
- 417. This configuration is equivalent to a simpler CxpCamera operator with only O output and no meta data.
- 418. This configuration is equivalent to a simpler CxpCamera operator with port O and MetaDataO selected.
- 419. In this configuration only the tap 0 is output with its metadata. For the tap 1 only the metadata is output. This configuration can be useful for debugging a camera/frame grabber combination.
- 420. In this configuration the operator provides both camera taps as 2 separate data streams on its Tap0 and Tap1 ports. However, no metadata information is output.
- 421. In this configuration the operator provides both camera taps as 2 separate streams on its Tap0 and Tap1 ports. The operator provides also the meta information for the Tap0 port. This configuration might be meaningful for symmetrical camera tap configurations, where the CXP header is in most parts identical for both taps except for the TapG Code fields.
- 422. This is the maximal configuration of the operator, where for each tap an own output is presented together with its own metadata.
- 423. LEDs on the imaFlex 2 Dual 100
- 424. FPGA Device Resources
- 425. FPGA Device Resources
- 426. FPGA Device Resources
- 427. FPGA Device Resources
- 428. FPGA Device Resources
- 429. FPGA Device Resources for imaFlex Platforms
- 430. FPGA Device Resources
- 431. Front GPIO Connector of the imaFlex 2 Dual 100
- 432. Extension GPIO Connector of the imaFlex 2 Dual 100
- 433. FPGA Device Resources
- 434. Front GPIO Connector of the imaFlex 2 Dual 100
- 435. Extension GPIO Connector of the imaFlex 2 Dual 100
- 436. FPGA Device Resources All Platforms Except imaFlex 2 Dual 100
- 437. FPGA Device Resources of imaFlex 2 Dual 100
- 438. LEDs on the imaFlex 2 Dual 100 Board
- 439. LEDs on the imaFlex CXP-12 Penta Board
- 440. LEDs on the imaFlex CXP-12 Quad Board
- 441. RAM architecture
- 442. imaFlex 2 Dual 100 C1 And C0 Connectors
- 443. QSFP28 Interface (illustrative)
- 444. Data Forwarding
- 445. Data Forwarding Port Connection
- 446. VA Design Example for a Master in a Data Forwarding Topology
- 447. VA Design Example for a Slave Master in a Data Forwarding Topology
- 448. VA Design Example for an Endpoint Slave Master in a Data Forwarding Topology
- 449. Daisy Chain (illustrative)
- 450. Dual Camera
- 451. Dual Master
- 452. Triple Master
List of Tables
- 1. Shortcut List for Main Program Window
- 2. Shortcut List for Simulation Viewer
- 3. Command Line Options and According Arguments
- 4. Operator Types
- 5. Availability of Autocompletion and Syntax Highlighting
- 6. List of Device Resources
- 7. Operator/Info
- 8. Operator/IO
- 9. Operator/Properties
- 10. Operator/ImgIn
- 11. Operator/ImgOut
- 12. Operator/RegIn
- 13. Operator/RegOut
- 14. Operator/Mem
- 15. Operator/Core
- 16. List of Basic Acquisition Examples
- 17. Data Forwarding Connections (Fiber Ports)
- 18. Message Bit Layout
- 19. List of Bayer Demosaicing Examples
- 20. Overview of Color Separation Examples
- 21. Design Versions for Grayscale JPEG Encoding
- 22. Design Versions for Color JPEG Encoding
- 23. List of Geometric Transformation Examples
- 24. Reading Cycles
- 25. Files and their corresponding lookup tables in Visual Applets
- 26. Examples of tap geometries
- 27. Available Libraries
- 28. Operators of Library Accumulator
- 29. Operators of Library Arithmetics
- 30. Operators of Library Base
- 31. Examples
- 32. Explanation of pseudo-code
- 33. Examples
- 34. Examples
- 35. Operators of Library Blob
- 36. Explanation of Blob Error Flags
- 37. Explanation of Blob Error Flags
- 38. Explanation of Blob Error Flags
- 39. Explanation of Blob Error Flags
- 40. Operators of Library Color
- 41. Operators of Library Compression
- 42. Operators of Library Debugging
- 43. Operators of Library Filter
- 44. Operators of Library Logic
- 45. Memory Types of Operators in the Library Memory
- 46. Individual Latencies of the Operators in Library Memory
- 47. Operators of Library Memory
- 48. Data types supported by reference operators
- 49. Operators of Library Parameters
- 50. Basic operations
- 51. Functions
- 52. Basic operations
- 53. Functions
- 54. Basic operations
- 55. Functions
- 56. Operators of Library Hardware Platform
- 57. Mapping VA notation and CL Specification Version 2.1
- 58.
- 59.
- 60.
- 61.
- 62. Mapping VA notation and CL Specification Version 2.1
- 63. Mapping VA notation and CL Specification Version 2.1
- 64. Operators of Library Prototype
- 65. Operators of Library Signal
- 66. Operators of Library Synchronization
- 67. Operators of Library Transformation
- 68. Hardware Configuration imaFlex platforms
- 69. Hardware Configuration microEnable 5 marathon
- 70. List of Device Resources imaFlex 2 Dual 100
- 71. List of Device Resources imaFlex CXP-12 Quad and imaFlex CXP-12 Penta
- 72. List of Device Resources microEnable 5 marathon
List of Equations
