Operator Library: Logic
The operator IS_Equal sets the output to a logical "1" if the value at the input link I is equal to the value of parameter Number, otherwise the output is "0".
To compare the values of two input links use operator CMP_Equal instead.
Link Parameter | Input Link I | Output Link O |
---|---|---|
Bit Width | [1, 63] unsigned, [2, 64] signed | 1 |
Arithmetic | {unsigned, signed} | unsigned |
Parallelism | any | as I |
Kernel Columns | any | as I |
Kernel Rows | any | as I |
Img Protocol | {VALT_IMAGE2D, VALT_LINE1D, VALT_PIXEL0D} | as I |
Color Format | VAF_GRAY | as I |
Color Flavor | FL_NONE | as I |
Max. Img Width | any | as I |
Max. Img Height | any | as I |
Number | |
---|---|
Type | static/dynamic read/write parameter |
Default | 0 |
Range | Same as range of input link I |
Value to compare the input link value with. |
ImplementationType | ||||
---|---|---|---|---|
Type | static write parameter | |||
Default | AUTO | |||
Range | (AUTO, EmbeddedALU, LUT) | |||
Parameter ImplementationType allows you to influence the implementation of the operator, i.e., to define which logic elements are used for implementing the operator. You can select one of the following values: AUTO: When the operator is instantiated, the optimal implementation strategy for the given FPGA architecture is selected automatically, based on the parametrization of the operator. EmbeddedALU: The operator uses embedded ALU elements of the FPGA. LUT: The operator uses the LUT elements of the FPGA.
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The use of operator IS_Equal is shown in the following examples:
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Examples - A high speed and robust laser line detection algorithm. The algorithm determines center of gravity coordinates to obtain sub-pixel resolution results.
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Example - Histogram thresholding
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Examples - Shows the usage of operator Blob_Analysis_1D in line scan applications.
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Examples - A grid is overlayed to the input images. The grid pixel value is determined from the input pixel value.